Inventor · disambiguated record
Rodney E. Hooker
Also filed as: HOOKER RODNEY · HOOKER RODNEY E
140 granted patents·7 pending applications·1,480 citations·filing 1999–2022
99Inventor score
Files withIP FIRST LLC47VIA TECH INC29VIA ALLIANCE SEMICONDUCTOR CO LTD24HENRY G GLENN19HOOKER RODNEY E13
Top patents by PatentIndex Score
147 records- 0197US6832296B2Microprocessor with repeat prefetch instructionIP FIRST LLC·Filed 2002·Granted Dec 14, 2004·143 cites·11 claims
- 0296US9811468B2Set associative cache memory with heterogeneous replacement policyVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Nov 7, 2017·43 cites·15 claims
- 0395US11467675B1Multi-component detection of gesturesFACEBOOK TECH LLC·Filed 2021·Granted Oct 11, 2022·9 cites·21 claims
- 0495US9389863B2Processor that performs approximate computing instructionsVIA TECH INC·Filed 2014·Granted Jul 12, 2016·30 cites·25 claims
- 0593US9043580B2Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)HENRY G GLENN·Filed 2012·Granted May 26, 2015·21 cites·18 claims
- 0692US6647489B1Compare branch instruction pairing within a single integer pipelineIP FIRST LLC·Filed 2000·Granted Nov 11, 2003·76 cites·29 claims
- 0791US8364902B2Microprocessor with repeat prefetch indirect instructionVIA TECH INC·Filed 2009·Granted Jan 29, 2013·24 cites·50 claims
- 0891US6681311B2Translation lookaside buffer that caches memory type informationIP FIRST LLC·Filed 2001·Granted Jan 20, 2004·71 cites·35 claims
- 0990US9891918B2Fractional use of prediction history storage for operating system routinesVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2015·Granted Feb 13, 2018·9 cites·20 claims
- 1090US8782348B2Microprocessor cache line evict arrayEDDY COLIN·Filed 2008·Granted Jul 15, 2014·27 cites·39 claims
- 1190US8392693B2Fast REP STOS using grabline operationsHENRY G GLENN·Filed 2010·Granted Mar 5, 2013·13 cites·34 claims
- 1290US8090931B2Microprocessor with fused store address/store data microinstructionCOL GERARD M·Filed 2008·Granted Jan 3, 2012·24 cites·12 claims
- 1389US7546446B2Selective interrupt suppressionIP FIRST LLC·Filed 2003·Granted Jun 9, 2009·65 cites·30 claims
- 1489US7529912B2Apparatus and method for instruction-level specification of floating point formatVIA TECH INC·Filed 2005·Granted May 5, 2009·21 cites·28 claims
- 1589US7065632B1Method and apparatus for speculatively forwarding storehit data in a hierarchical mannerIP FIRST LLC·Filed 2000·Granted Jun 20, 2006·65 cites·15 claims
- 1687US9972375B2Sanitize-aware DRAM controllerVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted May 15, 2018·8 cites·20 claims
- 1787US9898291B2Microprocessor with arm and X86 instruction length decodersVIA TECH INC·Filed 2015·Granted Feb 20, 2018·5 cites·22 claims
- 1887US9891927B2Inter-core communication via uncore RAMVIA TECH INC·Filed 2014·Granted Feb 13, 2018·4 cites·19 claims
- 1987US9569363B2Selective prefetching of physically sequential cache line to cache line that includes loaded page table entryVIA TECH INC·Filed 2015·Granted Feb 14, 2017·5 cites·21 claims
- 2087US9244686B2Microprocessor that translates conditional load/store instructions into variable number of microinstructionsHENRY G GLENN·Filed 2012·Granted Jan 26, 2016·10 cites·47 claims
- 2186US8533437B2Guaranteed prefetch instructionHENRY G GLENN·Filed 2010·Granted Sep 10, 2013·9 cites·29 claims
- 2286US7181596B2Apparatus and method for extending a microprocessor instruction setIP FIRST LLC·Filed 2002·Granted Feb 20, 2007·39 cites·29 claims
- 2386US6810466B2Microprocessor and method for performing selective prefetch based on bus activity levelIP FIRST LLC·Filed 2002·Granted Oct 26, 2004·42 cites·34 claims
- 2485US8930679B2Out-of-order execution microprocessor with reduced store collision load replay by making an issuing of a load instruction dependent upon a dependee instruction of a store instructionDAY MATTHEW DANIEL·Filed 2009·Granted Jan 6, 2015·15 cites·20 claims
- 2585US8880807B2Bounding box prefetcherVIA TECH INC·Filed 2014·Granted Nov 4, 2014·7 cites·23 claims
- 2685US8762649B2Bounding box prefetcherHOOKER RODNEY E·Filed 2011·Granted Jun 24, 2014·8 cites·40 claims
- 2783US6549985B1Method and apparatus for resolving additional load misses and page table walks under orthogonal stalls in a single pipeline processorI P FIRST LLC·Filed 2000·Granted Apr 15, 2003·34 cites·20 claims
- 2882US8234450B2Efficient data prefetching in the presence of load hitsGLOVER CLINTON THOMAS·Filed 2010·Granted Jul 31, 2012·6 cites·8 claims
- 2982US6622211B2Virtual set cache that redirects store data to correct virtual set to avoid virtual set store miss penaltyIP FIRST LLC·Filed 2001·Granted Sep 16, 2003·32 cites·33 claims
- 3081US9501286B2Microprocessor with ALU integrated into load unitCOL GERARD M·Filed 2009·Granted Nov 22, 2016·9 cites·38 claims
- 3181US9317288B2Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipelineHENRY G GLENN·Filed 2012·Granted Apr 19, 2016·6 cites·20 claims
- 3281US9274795B2Conditional non-branch instruction predictionHENRY G GLENN·Filed 2012·Granted Mar 1, 2016·6 cites·22 claims
- 3381US7191320B2Apparatus and method for performing a detached load operation in a pipeline microprocessorVIA TECH INC·Filed 2004·Granted Mar 13, 2007·33 cites·49 claims
- 3481US6553473B1Byte-wise tracking on write allocateIP FIRST LLC·Filed 2000·Granted Apr 22, 2003·30 cites·29 claims
- 3580US10127041B2Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resourcesVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Nov 13, 2018·2 cites·20 claims
- 3680US9652398B2Cache replacement policy that considers memory access typeVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted May 16, 2017·5 cites·18 claims
- 3780US8533438B2Store-to-load forwarding based on load/store address computation source information comparisonsHOOKER RODNEY E·Filed 2010·Granted Sep 10, 2013·6 cites·24 claims
- 3880US6338136B1Pairing of load-ALU-store with conditional branchIP FIRST LLC·Filed 1999·Granted Jan 8, 2002·89 cites·24 claims
- 3979US10423216B2Asymmetric multi-core processor with native switching mechanismVIA TECH INC·Filed 2013·Granted Sep 24, 2019·5 cites·9 claims
- 4079US8880851B2Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipelineHENRY G GLENN·Filed 2011·Granted Nov 4, 2014·4 cites·22 claims
- 4179US8433853B2Prefetching of next physically sequential cache line after cache line that includes loaded page table entryEDDY COLIN·Filed 2012·Granted Apr 30, 2013·4 cites·20 claims
- 4279US7562192B2Microprocessor, apparatus and method for selective prefetch retireIP FIRST LLC·Filed 2006·Granted Jul 14, 2009·6 cites·27 claims
- 4379US7111125B2Apparatus and method for renaming a data block within a cacheIP FIRST LLC·Filed 2003·Granted Sep 19, 2006·32 cites·25 claims
- 4478US9817764B2Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access typeVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Nov 14, 2017·4 cites·21 claims
- 4578US7827390B2Microprocessor with private microcode RAMVIA TECH INC·Filed 2008·Granted Nov 2, 2010·8 cites·29 claims
- 4678US7373483B2Mechanism for extending the number of registers in a microprocessorIP FIRST LLC·Filed 2002·Granted May 13, 2008·24 cites·25 claims
- 4777US9317301B2Microprocessor with boot indicator that indicates a boot ISA of the microprocessor as either the X86 ISA or the ARM ISAVIA TECH INC·Filed 2014·Granted Apr 19, 2016·3 cites·20 claims
- 4876US6985999B2Microprocessor and method for utilizing disparity between bus clock and core clock frequencies to prioritize cache line fill bus access requestsIP FIRST LLC·Filed 2002·Granted Jan 10, 2006·21 cites·34 claims
- 4975US9588845B2Processor that recovers from excessive approximate computing errorVIA TECH INC·Filed 2014·Granted Mar 7, 2017·3 cites·20 claims
- 5075US8161246B2Prefetching of next physically sequential cache line after cache line that includes loaded page table entryHOOKER RODNEY E·Filed 2009·Granted Apr 17, 2012·5 cites·11 claims
Showing the top 50 of 147 patent records by PatentIndex Score.
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