Inventor · disambiguated record
Ram Huggahalli
Also filed as: HUGGAHALLI RAM
14 granted patents·3 pending applications·155 citations·filing 2001–2017
92Inventor score
Top patents by PatentIndex Score
17 records- 0186US6785793B2Method and apparatus for memory access scheduling to reduce memory access latencyINTEL CORP·Filed 2001·Granted Aug 31, 2004·60 cites·56 claims
- 0280US7257693B2Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said systemINTEL CORP·Filed 2004·Granted Aug 14, 2007·28 cites·20 claims
- 0377US7502877B2Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor systemINTEL CORP·Filed 2007·Granted Mar 10, 2009·7 cites·17 claims
- 0474US8307105B2Message communication techniquesKING STEVEN·Filed 2011·Granted Nov 6, 2012·3 cites·20 claims
- 0574US7231470B2Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor systemINTEL CORP·Filed 2003·Granted Jun 12, 2007·17 cites·14 claims
- 0670US7512750B2Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of informationINTEL CORP·Filed 2003·Granted Mar 31, 2009·15 cites·33 claims
- 0768US8688868B2Steering data units to a consumerVASUDEVAN ANIL·Filed 2011·Granted Apr 1, 2014·2 cites·12 claims
- 0866US8645596B2Interrupt techniquesKUMAR AMIT·Filed 2008·Granted Feb 4, 2014·3 cites·25 claims
- 0963US7143238B2Mechanism to compress data in a cacheINTEL CORP·Filed 2003·Granted Nov 28, 2006·9 cites·37 claims
- 1062US8041854B2Steering data units to a consumerINTEL CORP·Filed 2007·Granted Oct 18, 2011·2 cites·20 claims
- 1162US7185147B2Striping across multiple cache lines to prevent false sharingINTEL CORP·Filed 2003·Granted Feb 27, 2007·9 cites·16 claims
- 1254US7996548B2Message communication techniquesINTEL CORP·Filed 2008·Granted Aug 9, 2011·0 cites·20 claims
- 1353US8751676B2Message communication techniquesKING STEVEN·Filed 2012·Granted Jun 10, 2014·0 cites·20 claims
- 1445US2006072563A1Packet processingREGNIER GREG J·Filed 2004·Application pending·0 cites
- 1544US11068399B2Technologies for enforcing coherence ordering in consumer polling interactions by receiving snoop request by controller and update value of cache lineINTEL CORP·Filed 2017·Granted Jul 20, 2021·0 cites·25 claims
- 1644US2009006668A1Performing direct data transactions with a cache memoryVASUDEVAN ANIL·Filed 2007·Application pending·0 cites
- 1741US2005246500A1Method, apparatus and system for an application-aware cache push agentIYER RAVISHANKAR·Filed 2004·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →