Inventor · disambiguated record
Steven J. Zier
Also filed as: ZIER STEVEN J · ZIER STEVEN JOHN
16 granted patents·3 pending applications·182 citations·filing 1987–2013
93Inventor score
Top patents by PatentIndex Score
19 records- 0188US7486114B2Signal detector with calibration circuit arrangementIBM·Filed 2006·Granted Feb 3, 2009·17 cites·35 claims
- 0288US7268624B2Differential amplifier offset voltage minimization independently from common mode voltage adjustmentIBM·Filed 2005·Granted Sep 11, 2007·20 cites·13 claims
- 0385US8126045B2System and method for latency reduction in speculative decision feedback equalizersBULZACCHELLI JOHN FRANCIS·Filed 2008·Granted Feb 28, 2012·17 cites·20 claims
- 0485US6528777B2Optical power meter derived from common-mode voltage of optical transimpedance amplifierIBM·Filed 2001·Granted Mar 4, 2003·30 cites·19 claims
- 0581US7394283B2CML to CMOS signal converterIBM·Filed 2006·Granted Jul 1, 2008·11 cites·7 claims
- 0681US6937054B2Programmable peaking receiver and methodIBM·Filed 2003·Granted Aug 30, 2005·34 cites·31 claims
- 0779US4746817ABIFET logic circuitIBM·Filed 1987·Granted May 24, 1988·29 cites·30 claims
- 0874US7660350B2High-speed multi-mode receiverIBM·Filed 2008·Granted Feb 9, 2010·5 cites·8 claims
- 0962US7205830B2Analog MOS circuits having reduced voltage stressIBM·Filed 2005·Granted Apr 17, 2007·5 cites·6 claims
- 1059US7694243B2Avoiding device stressingIBM·Filed 2007·Granted Apr 6, 2010·3 cites·5 claims
- 1158US8219040B2Transmitter bandwidth optimization circuitHSU LOUIS L·Filed 2007·Granted Jul 10, 2012·1 cites·16 claims
- 1246US8219041B2Design structure for transmitter bandwidth optimization circuitHSU LOUIS L·Filed 2007·Granted Jul 10, 2012·0 cites·4 claims
- 1346US7332956B2Method to avoid device stressingIBM·Filed 2005·Granted Feb 19, 2008·1 cites·19 claims
- 1444US5166552AMulti-emitter bicmos logic circuit family with superior performanceIBM·Filed 1988·Granted Nov 24, 1992·7 cites·43 claims
- 1541US7409019B2High Speed Multi-Mode Receiver with adaptive receiver equalization and controllable transmitter pre-distortionIBM·Filed 2004·Granted Aug 5, 2008·2 cites·6 claims
- 1640US2014184242A1In-Line Transistor Bandwidth MeasurementIBM·Filed 2013·Application pending·0 cites
- 1739US7265696B2Methods and apparatus for testing an integrated circuitIBM·Filed 2005·Granted Sep 4, 2007·0 cites·24 claims
- 1838US2009108885A1Design structure for CMOS differential rail-to-rail latch circuitsIBM·Filed 2007·Application pending·0 cites
- 1937US2008180139A1Cmos differential rail-to-rail latch circuitsIBM·Filed 2007·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →