Inventor · disambiguated record
Pierre-Emmanuel Gaillardon
Also filed as: GAILLARDON PIERRE-EMMANUEL · GAILLARDON PIERRE-EMMANUEL JULIEN · GAILLARDON PIERRE-EMMANUEL JULIEN MARC
12 granted patents·6 pending applications·38 citations·filing 2012–2024
85Inventor score
Files withUNIV UTAH RES FOUND7ECOLE POLYTECHNIQUE FED DE LAUSANNE (EPFL)3ECOLE POLYTECHNIQUE FED LAUSANNE EPFL3ECOLE POLYTECH2RAPIDSILICON US INC2
Top patents by PatentIndex Score
18 records- 0191US9412940B2Resistive switching element and use thereofECOLE POLYTECHNIQUE FED DE LAUSANNE (EPFL)·Filed 2013·Granted Aug 9, 2016·26 cites·8 claims
- 0271US11450385B2Digital RRAM-based convolutional blockUNIV UTAH RES FOUND·Filed 2019·Granted Sep 20, 2022·2 cites·20 claims
- 0368US9276573B2High-performance low-power near-Vt resistive memory-based FPGAECOLE POLYTECH·Filed 2014·Granted Mar 1, 2016·3 cites·8 claims
- 0462US9971862B2Pattern-based FPGA logic block and clustering algorithmECOLE POLYTECHNIQUE FED LAUSANNE EPFL·Filed 2015·Granted May 15, 2018·1 cites·7 claims
- 0561US8861254B2Memory cellGAILLARDON PIERRE-EMMANUEL·Filed 2012·Granted Oct 14, 2014·4 cites·22 claims
- 0659US10394988B2Majority logic synthesisECOLE POLYTECHNIQUE FED LAUSANNE EPFL·Filed 2014·Granted Aug 27, 2019·1 cites·12 claims
- 0757US12117316B2Resistive sensor interfaceUNIV UTAH RES FOUND·Filed 2023·Granted Oct 15, 2024·0 cites·20 claims
- 0857US9130568B2Controllable polarity FET based arithmetic and differential logicECOLE POLYTECH·Filed 2013·Granted Sep 8, 2015·1 cites·9 claims
- 0950US2024232129A1Programmable Compute ArchitectureRAPIDSILICON US INC·Filed 2023·Application pending·0 cites
- 1045US2023244906A13-branch deep neural networkUNIV UTAH RES FOUND·Filed 2022·Application pending·0 cites
- 1144US2023297748A1Hierarchical floor-planning for rapid fpga prototypingUNIV UTAH RES FOUND·Filed 2022·Application pending·0 cites
- 1244US2025080087A1Parasitic capacitance mitigation circuit for relaxation oscillatorsUNIV UTAH RES FOUND·Filed 2024·Application pending·0 cites
- 1342US9685959B2Method for speeding up boolean satisfiabilityECOLE POLYTECHNIQUE FED DE LAUSANNE (EPFL)·Filed 2015·Granted Jun 20, 2017·0 cites·4 claims
- 1439US2024232497A1Method for Generating Placement and Routing for an Integrated Circuit (IC)RAPIDSILICON US INC·Filed 2023·Application pending·0 cites
- 1538US12112820B2Single event effect mitigation with smart-redundancyUNIV UTAH RES FOUND·Filed 2021·Granted Oct 8, 2024·0 cites·18 claims
- 1637US11251881B2System for recursive calibration of a sensor networkUNIV UTAH RES FOUND·Filed 2020·Granted Feb 15, 2022·0 cites·20 claims
- 1737US2016322101A1Resistive Switching Element and Use ThereofECOLE POLYTECHNIQUE FED DE LAUSANNE (EPFL)·Filed 2016·Application pending·0 cites
- 1836US10380309B2Boolean logic optimization in majority-inverter graphsECOLE POLYTECHNIQUE FED LAUSANNE EPFL·Filed 2015·Granted Aug 13, 2019·0 cites·4 claims
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