Inventor · disambiguated record
Jay T. Young
Also filed as: YOUNG JAY T · YOUNG JAY THOMAS
19 granted patents·1 pending application·661 citations·filing 1995–2022
95Inventor score
Top patents by PatentIndex Score
20 records- 0196US7509617B1Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirementsXILINX INC·Filed 2005·Granted Mar 24, 2009·70 cites·20 claims
- 0295US5659484AFrequency driven layout and method for field programmable gate arraysXILINX INC·Filed 1995·Granted Aug 19, 1997·317 cites·23 claims
- 0394US7890917B1Method and apparatus for providing secure intellectual property cores for a programmable logic deviceXILINX INC·Filed 2008·Granted Feb 15, 2011·47 cites·20 claims
- 0485US7941777B1Generating a module interface for partial reconfiguration design flowsXILINX INC·Filed 2007·Granted May 10, 2011·13 cites·17 claims
- 0582US7600210B1Method and apparatus for modular circuit design for a programmable logic deviceXILINX INC·Filed 2005·Granted Oct 6, 2009·12 cites·18 claims
- 0682US5648913AFrequency driven layout system and method for field programmable gate arraysXILINX INC·Filed 1995·Granted Jul 15, 1997·97 cites·14 claims
- 0780US7249335B1Methods of routing programmable logic devices to minimize programming timeXILINX INC·Filed 2006·Granted Jul 24, 2007·9 cites·8 claims
- 0876US6760899B1Dedicated resource placement enhancementXILINX INC·Filed 2002·Granted Jul 6, 2004·24 cites·16 claims
- 0972US7673272B1Method and apparatus for generating an area constraint for a module in a programmable logic deviceXILINX INC·Filed 2007·Granted Mar 2, 2010·5 cites·20 claims
- 1072US7149997B1Routing with frame awareness to minimize device programming time and test costXILINX INC·Filed 2004·Granted Dec 12, 2006·17 cites·16 claims
- 1171US7058919B1Methods of generating test designs for testing specific routing resources in programmable logic devicesXILINX INC·Filed 2003·Granted Jun 6, 2006·15 cites·33 claims
- 1270US7299430B1Reducing design execution run time bit stream size for device testingXILINX INC·Filed 2005·Granted Nov 20, 2007·6 cites·20 claims
- 1369US8332788B1Generating a module interface for partial reconfiguration design flowsYOUNG JAY T·Filed 2011·Granted Dec 11, 2012·3 cites·18 claims
- 1467US6944809B2Methods of resource optimization in programmable logic devices to reduce test timeXILINX INC·Filed 2002·Granted Sep 13, 2005·13 cites·19 claims
- 1563US7480842B1Method and apparatus for reducing the number of test designs for device testingXILINX INC·Filed 2004·Granted Jan 20, 2009·9 cites·9 claims
- 1656US7143384B1Methods of routing programmable logic devices to minimize programming timeXILINX INC·Filed 2003·Granted Nov 28, 2006·4 cites·24 claims
- 1753US2024194645A1U-turn circuitry to convert inter-layer connections of an integrated circuit device to intra-layer connectionsXILINX INC·Filed 2022·Application pending·0 cites
- 1852US10715149B1Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvementsXILINX INC·Filed 2019·Granted Jul 14, 2020·0 cites·21 claims
- 1946US10467373B2Method of selecting routing resources in a multi-chip integrated circuit deviceXILINX INC·Filed 2018·Granted Nov 5, 2019·0 cites·20 claims
- 2042US8418221B1Methods of prioritizing routing resources to generate and evaluate test designs in programmable logic devicesYOUNG JAY T·Filed 2004·Granted Apr 9, 2013·0 cites·28 claims
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