Inventor · disambiguated record
Alexander E. Andreev
Also filed as: ANDREEV ALEXANDER · ANDREEV ALEXANDER E
177 granted patents·10 pending applications·6,615 citations·filing 1994–2015
99Inventor score
Top patents by PatentIndex Score
187 records- 0198US5777360AHexagonal field programmable gate array architectureLSI LOGIC CORP·Filed 1995·Granted Jul 7, 1998·338 cites·49 claims
- 0297US6026223AAdvanced modular cell placement system with overlap remover with minimal noiseFiled 1996·Granted Feb 15, 2000·269 cites·20 claims
- 0397US5822214ACAD for hexagonal architectureLSI LOGIC CORP·Filed 1995·Granted Oct 13, 1998·297 cites·5 claims
- 0496US6407434B1Hexagonal architectureLSI LOGIC CORP·Filed 1995·Granted Jun 18, 2002·245 cites·4 claims
- 0596US6182272B1Metal layer assignmentLSI LOGIC CORP·Filed 1998·Granted Jan 30, 2001·332 cites·32 claims
- 0696US5650653AMicroelectronic integrated circuit including triangular CMOS "nand" gate deviceLSI LOGIC CORP·Filed 1995·Granted Jul 22, 1997·175 cites·47 claims
- 0794US5811863ATransistors having dynamically adjustable characteristicsLSI LOGIC CORP·Filed 1995·Granted Sep 22, 1998·202 cites·47 claims
- 0893US8629548B1Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic nodeEASIC CORP·Filed 2012·Granted Jan 14, 2014·56 cites·20 claims
- 0993US6553370B1Flexible search engine having sorted binary search tree for perfect matchLSI LOGIC CORP·Filed 2000·Granted Apr 22, 2003·114 cites·27 claims
- 1093US6324674B2Method and apparatus for parallel simultaneous global and detail routingLSI LOGIC CORP·Filed 1998·Granted Nov 27, 2001·206 cites·36 claims
- 1193US5973376AArchitecture having diamond shaped or parallelogram shaped cellsLSI LOGIC CORP·Filed 1995·Granted Oct 26, 1999·157 cites·9 claims
- 1293US5742086AHexagonal DRAM arrayLSI LOGIC CORP·Filed 1995·Granted Apr 21, 1998·162 cites·40 claims
- 1392US6564211B1Fast flexible search engine for longest prefix matchLSI LOGIC CORP·Filed 2000·Granted May 13, 2003·80 cites·20 claims
- 1491US8677306B1Microcontroller controlled or direct mode controlled network-fabric on a structured ASICEASIC CORP·Filed 2012·Granted Mar 18, 2014·59 cites·19 claims
- 1591US6292929B2Advanced modular cell placement systemLSI LOGIC CORP·Filed 1999·Granted Sep 18, 2001·142 cites·22 claims
- 1691US6289495B1Method and apparatus for local optimization of the global routingLSI LOGIC CORP·Filed 1998·Granted Sep 11, 2001·166 cites·20 claims
- 1791US5889329ATri-directional interconnect architecture for SRAMLSI LOGIC CORP·Filed 1995·Granted Mar 30, 1999·135 cites·65 claims
- 1891US5578840AMicroelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal geometryLIS LOGIC CORP·Filed 1994·Granted Nov 26, 1996·188 cites·9 claims
- 1990US6067409AAdvanced modular cell placement systemLSI LOGIC CORP·Filed 1997·Granted May 23, 2000·153 cites·23 claims
- 2089US6253363B1Net routing using basis element decompositionLSI LOGIC CORP·Filed 1998·Granted Jun 26, 2001·153 cites·24 claims
- 2189US6230306B1Method and apparatus for minimization of process defects while routingLSI LOGIC CORP·Filed 1998·Granted May 8, 2001·148 cites·31 claims
- 2289US6175950B1Method and apparatus for hierarchical global routing descendLSI LOGIC CORP·Filed 1998·Granted Jan 16, 2001·157 cites·19 claims
- 2388US7913149B2Low complexity LDPC encoding algorithmLSI CORP·Filed 2006·Granted Mar 22, 2011·16 cites·4 claims
- 2488US5872380AHexagonal sense cell architectureLSI LOGIC CORP·Filed 1995·Granted Feb 16, 1999·106 cites·27 claims
- 2587US6412102B1Wire routing optimizationLSI LOGIC CORP·Filed 1998·Granted Jun 25, 2002·139 cites·33 claims
- 2687US6247167B1Method and apparatus for parallel Steiner tree routingLSI LOGIC CORP·Filed 1998·Granted Jun 12, 2001·131 cites·82 claims
- 2787US5898597AIntegrated circuit floor plan optimization systemLSI LOGIC CORP·Filed 1997·Granted Apr 27, 1999·133 cites·20 claims
- 2886US6123736AMethod and apparatus for horizontal congestion removalLSI LOGIC CORP·Filed 1997·Granted Sep 26, 2000·119 cites·44 claims
- 2985US6068662AMethod and apparatus for congestion removalLSI LOGIG CORP·Filed 1997·Granted May 30, 2000·129 cites·29 claims
- 3085US6058254AMethod and apparatus for vertical congestion removalLSI LOGIC CORP·Filed 1997·Granted May 2, 2000·118 cites·37 claims
- 3183US6587990B1Method and apparatus for formula area and delay minimizationLSI LOGIC CORP·Filed 2000·Granted Jul 1, 2003·36 cites·12 claims
- 3282US6735600B1Editing protocol for flexible search enginesLSI LOGIC CORP·Filed 2001·Granted May 11, 2004·35 cites·18 claims
- 3381US9024657B2Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smallerEASIC CORP·Filed 2012·Granted May 5, 2015·9 cites·18 claims
- 3481US7415686B2Memory timing model with back-annotatingLSI CORP·Filed 2005·Granted Aug 19, 2008·12 cites·25 claims
- 3581US6223332B1Advanced modular cell placement system with overlap remover with minimal noiseLSI LOGIC CORP·Filed 2000·Granted Apr 24, 2001·28 cites·21 claims
- 3680US6941533B2Clock tree synthesis with skew for memory devicesLSI LOGIC CORP·Filed 2002·Granted Sep 6, 2005·28 cites·22 claims
- 3780US6154874AMemory-saving method and apparatus for partitioning high fanout netsLSI LOGIC CORP·Filed 1998·Granted Nov 28, 2000·91 cites·28 claims
- 3880US6134702APhysical design automation system and process for designing integrated circuit chips using multiway partitioning with constraintsLSI LOGIC CORP·Filed 1997·Granted Oct 17, 2000·90 cites·22 claims
- 3979US8151160B1Configurable low-density parity-check decoder for LDPC codes of arbitrary block size and method of configuring the sameANDREEV ALEXANDER E·Filed 2008·Granted Apr 3, 2012·11 cites·19 claims
- 4079US6070108AMethod and apparatus for congestion driven placementLSI LOGIC CORP·Filed 1997·Granted May 30, 2000·84 cites·16 claims
- 4178US5789770AHexagonal architecture with triangular shaped cellsLSI LOGIC CORP·Filed 1995·Granted Aug 4, 1998·53 cites·41 claims
- 4277US8735857B2Via-configurable high-performance logic block architectureANDREEV ALEXANDER·Filed 2011·Granted May 27, 2014·5 cites·14 claims
- 4377US7934139B2Parallel LDPC decoderLSI CORP·Filed 2006·Granted Apr 26, 2011·9 cites·2 claims
- 4477US6941494B1Built-in test for multiple memory circuitsLSI LOGIC CORP·Filed 2001·Granted Sep 6, 2005·24 cites·22 claims
- 4577US5808330APolydirectional non-orthoginal three layer interconnect architectureLSI LOGIC CORP·Filed 1995·Granted Sep 15, 1998·54 cites·12 claims
- 4676US7818703B2Density driven layout for RRAM configuration moduleLSI CORP·Filed 2007·Granted Oct 19, 2010·6 cites·14 claims
- 4775US7039855B2Decision function generator for a Viterbi decoderLSI LOGIC CORP·Filed 2003·Granted May 2, 2006·20 cites·18 claims
- 4875US7035844B2FFS search and edit pipeline separationLSI LOGIC CORP·Filed 2002·Granted Apr 25, 2006·20 cites·30 claims
- 4975US6487698B1Process, apparatus and program for transforming program language description of an IC to an RTL descriptionLSI LOGIC CORP·Filed 2001·Granted Nov 26, 2002·21 cites·20 claims
- 5073US8957398B2Via-configurable high-performance logic block involving transistor chainsEASIC CORP·Filed 2012·Granted Feb 17, 2015·4 cites·14 claims
Showing the top 50 of 187 patent records by PatentIndex Score.
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