Inventor · disambiguated record
Christine M. Desnoyers
Also filed as: DESNOYERS CHRISTINE M · DESNOYERS CHRISTINE MARIE
15 granted patents·449 citations·filing 1993–1997
95Inventor score
Files withIBM15
Top patents by PatentIndex Score
15 records- 0189US5508968ADynamic random access memory persistent page implemented as processor register setsIBM·Filed 1994·Granted Apr 16, 1996·59 cites·4 claims
- 0282US5363484AMultiple computer system with combiner/memory interconnection system employing separate direct access link for transferring information packetsIBM·Filed 1993·Granted Nov 8, 1994·115 cites·19 claims
- 0373US6337852B1Flow control system using control information of a message for initiating retransmission of data portion when buffer is availableIBM·Filed 1997·Granted Jan 8, 2002·47 cites·17 claims
- 0466US5594918AParallel computer system providing multi-ported intelligent memoryIBM·Filed 1995·Granted Jan 14, 1997·49 cites·16 claims
- 0565US5968189ASystem of reporting errors by a hardware element of a distributed computer systemIBM·Filed 1997·Granted Oct 19, 1999·60 cites·7 claims
- 0652US6480897B1Optimistic transmission flow control including receiver data discards upon inadequate buffering conditionIBM·Filed 1997·Granted Nov 12, 2002·18 cites·19 claims
- 0752US5923840AMethod of reporting errors by a hardware element of a distributed computer systemIBM·Filed 1997·Granted Jul 13, 1999·27 cites·6 claims
- 0847US6185693B1Synchronous interface for transmitting data in a system of massively parallel processorsIBM·Filed 1996·Granted Feb 6, 2001·17 cites·3 claims
- 0942US6105071ASource and destination initiated interrupt system for message arrival notificationIBM·Filed 1997·Granted Aug 15, 2000·14 cites·18 claims
- 1042US5694612ASelf-timed interface for a network of computer processors interconnected in parallelIBM·Filed 1996·Granted Dec 2, 1997·12 cites·4 claims
- 1142US5555528ADynamic random access memory persistent page implemented as processor register setsIBM·Filed 1995·Granted Sep 10, 1996·6 cites·4 claims
- 1240US6098105ASource and destination initiated interrupt method for message arrival notificationIBM·Filed 1997·Granted Aug 1, 2000·13 cites·27 claims
- 1337US6338091B1System for optimistic transmission flow control including receiver data discards upon inadequate buffering conditionIBM·Filed 1997·Granted Jan 8, 2002·6 cites·19 claims
- 1433US5519664ADynamic random access memory persistent page implemented as processor register setsIBM·Filed 1995·Granted May 21, 1996·4 cites·2 claims
- 1531US6098104ASource and destination initiated interrupts for message arrival notification, and related data structuresIBM·Filed 1997·Granted Aug 1, 2000·2 cites·11 claims
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