Inventor · disambiguated record
Etai Adar
Also filed as: ADAR ETAI
20 granted patents·2 pending applications·107 citations·filing 1998–2017
93Inventor score
Top patents by PatentIndex Score
22 records- 0193US9715470B1Direct memory access between an accelerator and a processor using a coherency adapterIBM·Filed 2016·Granted Jul 25, 2017·9 cites·20 claims
- 0289US8489787B2Sharing sampled instruction address registers for efficient instruction sampling in massively multithreaded processorsADAR ETAI·Filed 2010·Granted Jul 16, 2013·14 cites·14 claims
- 0384US9086965B2PCI express error handling and recovery action controlsADAR ETAI·Filed 2011·Granted Jul 21, 2015·9 cites·12 claims
- 0482US7562168B1Method of optimizing buffer usage of virtual channels of a physical communication link and apparatuses for performing the sameIBM·Filed 2008·Granted Jul 14, 2009·15 cites·1 claims
- 0581US10169247B2Direct memory access between an accelerator and a processor using a coherency adapterIBM·Filed 2017·Granted Jan 1, 2019·2 cites·20 claims
- 0681US8589922B2Performance monitor design for counting events generated by thread groupsADAR ETAI·Filed 2010·Granted Nov 19, 2013·7 cites·13 claims
- 0777US10394711B2Managing lowest point of coherency (LPC) memory using a service layer adapterIBM·Filed 2016·Granted Aug 27, 2019·2 cites·20 claims
- 0877US9032102B2Decode data for fast PCI express multi-function device address decodeGRANOVSKY ILYA·Filed 2012·Granted May 12, 2015·7 cites·20 claims
- 0974US9892061B1Direct memory access between an accelerator and a processor using a coherency adapterIBM·Filed 2017·Granted Feb 13, 2018·1 cites·20 claims
- 1074US7827325B2Device, system, and method of speculative packet transmissionIBM·Filed 2007·Granted Nov 2, 2010·7 cites·13 claims
- 1167US7734854B2Device, system, and method of handling transactionsIBM·Filed 2008·Granted Jun 8, 2010·4 cites·12 claims
- 1266US8601193B2Performance monitor design for instruction profiling using shared countersADAR ETAI·Filed 2010·Granted Dec 3, 2013·2 cites·19 claims
- 1365US10296253B2Coordination of spare lane usage between link partnersIBM·Filed 2016·Granted May 21, 2019·1 cites·12 claims
- 1457US8249177B2Detection of frame marker qualityADAR ETAI·Filed 2009·Granted Aug 21, 2012·1 cites·18 claims
- 1553US8024597B2Signal phase verification for systems incorporating two synchronous clock domainsIBM·Filed 2008·Granted Sep 20, 2011·1 cites·20 claims
- 1652US9354990B2Coordination of spare lane usage between link partnersIBM·Filed 2014·Granted May 31, 2016·0 cites·12 claims
- 1746US6611211B2Data mask codingIBM·Filed 2001·Granted Aug 26, 2003·3 cites·19 claims
- 1845US2009187683A1Adaptive link width controlIBM·Filed 2008·Application pending·0 cites
- 1944US7747803B2Device, system, and method of handling delayed transactionsIBM·Filed 2007·Granted Jun 29, 2010·0 cites·3 claims
- 2043US6021483APCI-to-PCI bridges with a timer register for storing a delayed transaction latencyIBM·Filed 1998·Granted Feb 1, 2000·22 cites·7 claims
- 2143US2009185487A1Automated advance link activationIBM·Filed 2008·Application pending·0 cites
- 2242US8417851B2Polling of a target register within a peripheral deviceADAR ETAI·Filed 2011·Granted Apr 9, 2013·0 cites·14 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →