Inventor · disambiguated record
Jiayong Le
Also filed as: LE JIAYONG
13 granted patents·1 pending application·272 citations·filing 2005–2024
90Inventor score
Technology areasG06F
Top patents by PatentIndex Score
14 records- 0196US7890915B2Statistical delay and noise calculation considering cell and interconnect variationsCELIK MUSTAFA·Filed 2006·Granted Feb 15, 2011·190 cites·6 claims
- 0291US8843864B2Statistical corner evaluation for complex on-chip variation modelSYNOPSYS INC·Filed 2013·Granted Sep 23, 2014·18 cites·21 claims
- 0389US8713501B1Dual-box location aware and dual-bitmap voltage domain aware on-chip variation techniquesSYNOPSYS INC·Filed 2012·Granted Apr 29, 2014·14 cites·23 claims
- 0489US8407640B2Sensitivity-based complex statistical modeling for random on-chip variationLE JIAYONG·Filed 2011·Granted Mar 26, 2013·18 cites·8 claims
- 0586US7487486B2Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variationsCELIK MUSTAFA·Filed 2005·Granted Feb 3, 2009·18 cites·8 claims
- 0684US8555222B2Statistical corner evaluation for complex on chip variation modelLE JIAYONG·Filed 2013·Granted Oct 8, 2013·9 cites·12 claims
- 0775US8495544B2Statistical delay and noise calculation considering cell and interconnect variationsCELIK MUSTAFA·Filed 2010·Granted Jul 23, 2013·5 cites·21 claims
- 0871US2025077752A1Method to compute timing yield and yield bottleneck using correlated sample generation and efficient statistical simulationSYNOPSYS INC·Filed 2024·Application pending·0 cites
- 0965US11288426B2Analyzing delay variations and transition time variations for electronic circuitsSYNOPSYS INC·Filed 2020·Granted Mar 29, 2022·0 cites·20 claims
- 1061US10783301B2Analyzing delay variations and transition time variations for electronic circuitsSYNOPSYS INC·Filed 2019·Granted Sep 22, 2020·0 cites·20 claims
- 1157US12112108B2Method to compute timing yield and yield bottleneck using correlated sample generation and efficient statistical simulationSYNOPSYS INC·Filed 2020·Granted Oct 8, 2024·0 cites·10 claims
- 1253US10255395B2Analyzing delay variations and transition time variations for electronic circuitsSYNOPSYS INC·Filed 2016·Granted Apr 9, 2019·0 cites·23 claims
- 1349US9424380B2Augmented simulation method for waveform propagation in delay calculationSYNOPSYS INC·Filed 2014·Granted Aug 23, 2016·0 cites·19 claims
- 1448US10755023B1Circuit timing analysisSYNOPSYS INC·Filed 2018·Granted Aug 25, 2020·0 cites·21 claims
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