Inventor · disambiguated record
Alexey Y. Sivtsov
Also filed as: SIVTSOV ALEXEY · SIVTSOV ALEXEY Y · SIVTSOV ALEXEY YURIEVICH
4 granted patents·5 pending applications·6 citations·filing 2006–2021
64Inventor score
Technology areasG06F
Top patents by PatentIndex Score
9 records- 0165US9645819B2Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processorIYER JAYESH·Filed 2012·Granted May 9, 2017·3 cites·30 claims
- 0262US9632790B2Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program orderINTEL CORP·Filed 2012·Granted Apr 25, 2017·2 cites·21 claims
- 0353US9529596B2Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bitsBABAYAN BORIS A·Filed 2011·Granted Dec 27, 2016·1 cites·12 claims
- 0452US12430135B2Device, method, and system to facilitate improved bandwidth of a branch prediction unitINTEL CORP·Filed 2021·Granted Sep 30, 2025·0 cites·20 claims
- 0548US2017235578A1Method and Apparatus for Scheduling of Instructions in a Multi-Strand Out-Of-Order ProcessorINTEL CORP·Filed 2016·Application pending·0 cites
- 0646US2021200550A1Loop exit predictorINTEL CORP·Filed 2019·Application pending·0 cites
- 0742US2016364237A1Processor logic and method for dispatching instructions from multiple strandsINTEL CORP·Filed 2014·Application pending·0 cites
- 0838US2008133895A1Floating Point AdditionSIVTSOV ALEXEY YURIEVICH·Filed 2006·Application pending·0 cites
- 0933US2014208074A1Instruction scheduling for a multi-strand out-of-order processorBABAYAN BORIS A·Filed 2012·Application pending·0 cites
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