Inventor · disambiguated record
Sergey Y. Shishlov
Also filed as: SHISHLOV SERGEY · SHISHLOV SERGEY Y · SHISHLOV SERGEY YU
8 granted patents·7 pending applications·22 citations·filing 2009–2016
81Inventor score
Technology areasG06F
Top patents by PatentIndex Score
15 records- 0182US10514927B2Instruction and logic for sorting and retiring storesINTEL CORP·Filed 2014·Granted Dec 24, 2019·11 cites·20 claims
- 0270US10133582B2Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processorINTEL CORP·Filed 2013·Granted Nov 20, 2018·3 cites·20 claims
- 0368US10095623B2Hardware apparatuses and methods to control access to a multiple bank data cacheINTEL CORP·Filed 2016·Granted Oct 9, 2018·1 cites·24 claims
- 0465US9645819B2Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processorIYER JAYESH·Filed 2012·Granted May 9, 2017·3 cites·30 claims
- 0563US9471501B2Hardware apparatuses and methods to control access to a multiple bank data cacheINTEL CORP·Filed 2014·Granted Oct 18, 2016·1 cites·24 claims
- 0662US9632790B2Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program orderINTEL CORP·Filed 2012·Granted Apr 25, 2017·2 cites·21 claims
- 0753US9529596B2Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bitsBABAYAN BORIS A·Filed 2011·Granted Dec 27, 2016·1 cites·12 claims
- 0848US2017235578A1Method and Apparatus for Scheduling of Instructions in a Multi-Strand Out-Of-Order ProcessorINTEL CORP·Filed 2016·Application pending·0 cites
- 0945US2010274972A1Systems, methods, and apparatuses for parallel computingBABAYAN BORIS·Filed 2009·Application pending·0 cites
- 1044US2016306742A1Instruction and logic for memory access in a clustered wide-execution machineINTEL CORP·Filed 2013·Application pending·0 cites
- 1142US2016364237A1Processor logic and method for dispatching instructions from multiple strandsINTEL CORP·Filed 2014·Application pending·0 cites
- 1233US2014208074A1Instruction scheduling for a multi-strand out-of-order processorBABAYAN BORIS A·Filed 2012·Application pending·0 cites
- 1332US9811340B2Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processorKOSAREV NIKOLAY·Filed 2012·Granted Nov 7, 2017·0 cites·21 claims
- 1432US2017161075A1Increasing processor instruction window via seperating instructions according to criticalityINTEL CORP·Filed 2015·Application pending·0 cites
- 1530US2018285119A1Apparatus and method for inter-strand communicationINTEL CORP·Filed 2015·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →