Inventor

BOSE PRADIP

US157 patents

⚠️ This page may combine multiple inventors who share the name “BOSE PRADIP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOSE PRADIP

IBM

Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Method and system for controlling power in a chip through a power-performance monitor and control unit

Cognitive computing for servers and mobile devices

Cognitive computing for servers and mobile devices

Interlocked synchronous pipeline clock gating

Performance evaluation of processor operation using trace pre-processing

Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Method of virtualization and OS-level thermal management and multithreaded processor with virtualization and OS-level thermal management

Interlocked synchronous pipeline clock gating

Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system

Method and apparatus for extending lifetime reliability of digital logic devices through reversal of aging mechanisms

Processor with low overhead predictive supply voltage gating for leakage power reduction

Method and structure for short range leakage control in pipelined circuits

Method and apparatus for monitoring and enhancing on-chip microprocessor reliability

Processor with demand-driven clock throttling power reduction

Method and system for reducing average branch resolution time and effective misprediction penalty in a processor

On-chip supply noise voltage reduction or mitigation using local detection loops in a processor core

Generation and application of stressmarks in a computer system

Silent store detection and recording in memory storage

Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Dynamic detection of resource management anomalies in a processing system

Method and system of multi-core microprocessor power management and control via per-chiplet, programmable power modes

Adaptive issue queue for reduced power at high performance

Method for extending lifetime reliability of digital logic devices through reversal of aging mechanisms

Methods for thermal management of three-dimensional integrated circuits

Method of predicting microprocessor lifetime reliability using architecture-level structure-aware techniques

Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power

Interlocked synchronous pipeline clock gating

Inducing heterogeneous microprocessor behavior using non-uniform cooling

Dynamic adjustments within memory systems

Proactive voltage droop reduction and/or mitigation in a processor core

Inducing heterogeneous microprocessor behavior using non-uniform cooling

Method and system of peak power enforcement via autonomous token-based control and management

Determination and correction of physical circuit event related errors of a hardware design

Processor register error correction management

BOSE PRADIP

Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip

Systems and methods for thread assignment and core turn-off for integrated circuit energy efficiency and high-performance

Method and system for controlling power in a chip through a power-performance monitor and control unit

Method and system for controlling power in a chip through a power performance monitor and control unit

Low overhead dynamic thermal management in many-core cluster architecture

Vertical power budgeting and shifting for three-dimensional integration

Managing instructions for more efficient load/store unit usage

Adaptive data prefetch

Modeling system-level effects of soft errors

Adaptive workload based optimizations to mitigate current delivery limitations in integrated circuits

Guarded, multi-metric resource control for safe and efficient microprocessor management

Hardware execution driven application level derating calculation for soft error rate analysis

BASAK JAYANTA

Predictive power gating with optional guard mechanism

Two-level guarded predictive power gating