Inventor · disambiguated record
Sergey A. Rozhkov
Also filed as: ROZHKOV SERGEY A
9 granted patents·4 pending applications·72 citations·filing 2001–2016
84Inventor score
Technology areasG06F
Top patents by PatentIndex Score
13 records- 0183US7143401B2Single-chip multiprocessor with cycle-precise program scheduling of parallel executionELBRUS INTERNAT·Filed 2001·Granted Nov 28, 2006·40 cites·6 claims
- 0274US8261250B2Single-chip multiprocessor with clock cycle-precise program scheduling of parallel executionBABAIAN BORIS A·Filed 2011·Granted Sep 4, 2012·5 cites·4 claims
- 0369US7065750B2Method and apparatus for preserving precise exceptions in binary translated codeELBRUS INTERNAT·Filed 2001·Granted Jun 20, 2006·24 cites·18 claims
- 0465US7895587B2Single-chip multiprocessor with clock cycle-precise program scheduling of parallel executionELBRUS INTERNAT·Filed 2006·Granted Feb 22, 2011·3 cites·17 claims
- 0550US10579378B2Instructions for manipulating a multi-bit predicate register for predicating instruction sequencesINTEL CORP·Filed 2014·Granted Mar 3, 2020·0 cites·24 claims
- 0646US10235171B2Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processorINTEL CORP·Filed 2016·Granted Mar 19, 2019·0 cites·20 claims
- 0745US2010274972A1Systems, methods, and apparatuses for parallel computingBABAYAN BORIS·Filed 2009·Application pending·0 cites
- 0845US2016055004A1Method and apparatus for non-speculative fetch and execution of control-dependent blocksGROCHOWSKI EDWARD T·Filed 2014·Application pending·0 cites
- 0944US10241801B2Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop acceleratorINTEL CORP·Filed 2016·Granted Mar 26, 2019·0 cites·22 claims
- 1043US10241794B2Apparatus and methods to support counted loop exits in a multi-strand loop processorINTEL CORP·Filed 2016·Granted Mar 26, 2019·0 cites·20 claims
- 1143US10241789B2Method to do control speculation on loads in a high performance strand-based loop acceleratorINTEL CORP·Filed 2016·Granted Mar 26, 2019·0 cites·20 claims
- 1236US2018181398A1Apparatus and methods of decomposing loops to improve performance and power efficiencyINTEL CORP·Filed 2016·Application pending·0 cites
- 1335US2017090929A1Hardware-assisted software verification and secure executionMCAFEE INC·Filed 2015·Application pending·0 cites
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