Inventor

GADRE SHIRISH

US72 patents

⚠️ This page may combine multiple inventors who share the name “GADRE SHIRISH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GADRE SHIRISH

NVIDIA CORP

Techniques for efficiently transferring data to a processor

Technique for accessing content-addressable memory

Method and apparatus for obtaining sampled positions of texturing operations

Method and apparatus for obtaining sampled positions of texturing operations

System and processor that include an implementation of decoupled pipelines

Selective fault stalling for a GPU memory pipeline in a unified virtual memory system

Method and apparatus for efficient access to multidimensional data structures and/or other large data blocks

Programmatically controlled data multicasting across multiple compute engines

High performance synchronization mechanisms for coordinating operations on a computer system

Unified cache for diverse memory traffic

System, method, and computer program product for implementing software-based scoreboarding

Approach for context switching of lock-bit protected memory

Binding constants at runtime for improved resource utilization

Method and apparatus for efficient access to multidimensional data structures and/or other large data blocks

Hybrid allocation of data lines in a streaming cache memory

Techniques for efficiently transferring data to a processor

Techniques for efficiently transferring data to a processor

Unified cache for diverse memory traffic

Cooperative thread array granularity context switch during trap handling

Implementing specialized instructions for accelerating Smith-Waterman sequence alignments

Simultaneous compute and graphics scheduling

Cooperative group arrays

Distributed shared memory

Out of order memory request tracking structure and technique

Techniques for performing accelerated point sampling in a texture processing pipeline

Efficient execution of atomic instructions for single instruction, multiple thread (SIMT) architectures

Cache memory with per-sector cache residency controls

SONY CORP

Distributed extensible processing architecture for digital signal processing applications

RISC CPU instructions particularly suited for decoding digital signal processing applications

System and method for flexibly blending multiple image planes in a video device

Decoder system with 2.53 frame display buffer

Display unit architecture

Video content scene change determination

KARANDIKAR ASHISH

Methods and systems for command acceleration in a video processor via translation of scalar instructions into vector instructions

Context switching on a video processor having a scalar execution unit and a vector execution unit

Latency tolerant system for executing video processing operations

Pipelined L2 cache for memory transfers for a video processor

Multidimensional datapath processing in a video processor

GADRE SHIRISH

N-way memory barrier operation coalescing

Stream processing in a video processor

Data path and instruction set for packed pixel operations for video processing

Video processor having scalar and vector components

SONY ELECTRONICS INC

Memory controller providing dynamic arbitration of memory commands

Multifunctional I/O organizer unit for multiprocessor multimedia chips

Method and apparatus for efficiently allocating memory when switching between DVD audio and DVD video

Method and apparatus for efficiently allocating memory in audio still video (ASV) applications

LEW STEPHEN D

Programmable DMA engine for implementing memory transfers and video processing for a video processor

Multi context execution on a video processor

FETTERMAN MICHAEL

Dynamic bank mode addressing for memory access

Mechanism for waking common resource requests within a resource management subsystem