Inventor · disambiguated record
Xiaogang Qiu
Also filed as: QIU XIAOGANG
23 granted patents·70 citations·filing 2003–2023
94Inventor score
Top patents by PatentIndex Score
23 records- 0192US11080051B2Techniques for efficiently transferring data to a processorNVIDIA CORP·Filed 2019·Granted Aug 3, 2021·9 cites·26 claims
- 0289US8321761B1ECC bits used as additional register file storageGRUNER FRED·Filed 2009·Granted Nov 27, 2012·9 cites·19 claims
- 0387US9471307B2System and processor that include an implementation of decoupled pipelinesNVIDIA CORP·Filed 2014·Granted Oct 18, 2016·10 cites·16 claims
- 0481US11803380B2High performance synchronization mechanisms for coordinating operations on a computer systemNVIDIA CORP·Filed 2019·Granted Oct 31, 2023·2 cites·22 claims
- 0580US10459861B2Unified cache for diverse memory trafficNVIDIA CORP·Filed 2017·Granted Oct 29, 2019·2 cites·21 claims
- 0679US9612836B2System, method, and computer program product for implementing software-based scoreboardingNVIDIA CORP·Filed 2014·Granted Apr 4, 2017·5 cites·19 claims
- 0777US9477482B2System, method, and computer program product for implementing multi-cycle register file bypassNVIDIA CORP·Filed 2013·Granted Oct 25, 2016·4 cites·20 claims
- 0875US9971699B2Method to control cache replacement for decoupled data fetchNVIDIA CORP·Filed 2016·Granted May 15, 2018·2 cites·20 claims
- 0975US8533435B2Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflictQIU XIAOGANG·Filed 2010·Granted Sep 10, 2013·4 cites·19 claims
- 1069US11604649B2Techniques for efficiently transferring data to a processorNVIDIA CORP·Filed 2021·Granted Mar 14, 2023·0 cites·11 claims
- 1167US7484039B2Method and apparatus for implementing a grid storage systemQIU XIAOGANG·Filed 2006·Granted Jan 27, 2009·7 cites·3 claims
- 1266US11347668B2Unified cache for diverse memory trafficNVIDIA CORP·Filed 2020·Granted May 31, 2022·0 cites·20 claims
- 1366US9830158B2Speculative execution and rollbackCHOQUETTE JACK HILAIRE·Filed 2011·Granted Nov 28, 2017·2 cites·28 claims
- 1463US11907717B2Techniques for efficiently transferring data to a processorNVIDIA CORP·Filed 2023·Granted Feb 20, 2024·0 cites·21 claims
- 1563US8250439B1ECC bits used as additional register file storageGRUNER FRED·Filed 2009·Granted Aug 21, 2012·2 cites·20 claims
- 1661US10255228B2System and method for performing shaped memory access operationsQIU XIAOGANG·Filed 2011·Granted Apr 9, 2019·1 cites·7 claims
- 1761US9626191B2Shaped register file readsCHOQUETTE JACK HILAIRE·Filed 2011·Granted Apr 18, 2017·1 cites·20 claims
- 1857US10705994B2Unified cache for diverse memory trafficNVIDIA CORP·Filed 2017·Granted Jul 7, 2020·0 cites·20 claims
- 1956US7509643B2Method and apparatus for supporting asymmetric multi-threading in a computer systemSUN MICROSYSTEMS INC·Filed 2003·Granted Mar 24, 2009·7 cites·12 claims
- 2051US7188324B1Assertion morphing in functional verification of integrated circuit designSUN MICROSYSTEMS INC·Filed 2004·Granted Mar 6, 2007·3 cites·7 claims
- 2149US10489200B2Hierarchical staging areas for scheduling threads for executionNVIDIA CORP·Filed 2013·Granted Nov 26, 2019·0 cites·24 claims
- 2248US9798544B2Reordering buffer for memory access localityNVIDIA CORP·Filed 2012·Granted Oct 24, 2017·0 cites·23 claims
- 2338US9606808B2Method and system for resolving thread divergencesCHOQUETTE JACK·Filed 2012·Granted Mar 28, 2017·0 cites·22 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →