Assignee
MAHER MONIER
US·1 granted patent·1 pending application·20 citations·filing 2004–2008
Technology mixG06F2
Top patents by PatentIndex Score
2 records- 0184US8180998B1System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operationsMAHER MONIER·Filed 2008·Granted May 15, 2012·20 cites·18 claims
- 0241US2005251644A1Physics processing unit instruction set architectureMAHER MONIER·Filed 2004·Application pending·0 cites
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