Assignee
ASCENIUM INC
US·4 granted patents·28 pending applications·0 citations·filing 2018–2025
Top patents by PatentIndex Score
32 records- 0161US12493554B2Parallel processing using hazard detection and mitigationASCENIUM INC·Filed 2023·Granted Dec 9, 2025·0 cites·25 claims
- 0259US2025383878A1Memory dependence prediction in a parallel architecture with compute slicesASCENIUM INC·Filed 2025·Application pending·0 cites
- 0357US12504958B2Compute element processing using control word templatesASCENIUM INC·Filed 2022·Granted Dec 23, 2025·0 cites·24 claims
- 0456US2024419507A1Parallel processing architecture with block move backpressureASCENIUM INC·Filed 2024·Application pending·0 cites
- 0556US2024385965A1Parallel processing architecture with block move supportASCENIUM INC·Filed 2024·Application pending·0 cites
- 0655US12578991B2Parallel processing architecture with distributed register filesASCENIUM INC·Filed 2022·Granted Mar 17, 2026·0 cites·19 claims
- 0755US11531638B2Reconfigurable circuit array using instructions including a fetch configuration data portion and a transfer configuration data portionASCENIUM INC·Filed 2018·Granted Dec 20, 2022·0 cites·14 claims
- 0855US2024264974A1Parallel processing hazard mitigation avoidanceASCENIUM INC·Filed 2024·Application pending·0 cites
- 0954US2024168802A1Parallel processing with hazard detection and store probesASCENIUM INC·Filed 2024·Application pending·0 cites
- 1054US2024193009A1Parallel processing architecture for branch path suppressionASCENIUM INC·Filed 2024·Application pending·0 cites
- 1153US2024078182A1Parallel processing with switch block executionASCENIUM INC·Filed 2023·Application pending·0 cites
- 1253US2022107812A1Highly parallel processing architecture using dual branch executionASCENIUM INC·Filed 2021·Application pending·0 cites
- 1352US2023376447A1Parallel processing architecture with dual load buffersASCENIUM INC·Filed 2023·Application pending·0 cites
- 1452US2023409328A1Parallel processing architecture with memory block transfersASCENIUM INC·Filed 2023·Application pending·0 cites
- 1551US2023350713A1Parallel processing architecture with countdown taggingASCENIUM INC·Filed 2023·Application pending·0 cites
- 1651US2023281014A1Parallel processing of multiple loops with loads and storesASCENIUM INC·Filed 2023·Application pending·0 cites
- 1751US2023342152A1Parallel processing architecture with split control word cachesASCENIUM INC·Filed 2023·Application pending·0 cites
- 1851US2025265088A1Compiler generated hyperblocks in a parallel architecture with compute slicesASCENIUM INC·Filed 2025·Application pending·0 cites
- 1950US2023221931A1Autonomous compute element operation using buffersASCENIUM INC·Filed 2023·Application pending·0 cites
- 2050US2023273818A1Highly parallel processing architecture with out-of-order resolutionASCENIUM INC·Filed 2023·Application pending·0 cites
- 2149US2025021405A1Parallel architecture with compiler-scheduled compute slicesASCENIUM INC·Filed 2024·Application pending·0 cites
- 2248US2023031902A1Load latency amelioration using bunch buffersASCENIUM INC·Filed 2022·Application pending·0 cites
- 2348US2022374286A1Parallel processing architecture for atomic operationsASCENIUM INC·Filed 2022·Application pending·0 cites
- 2447US2022308872A1Parallel processing architecture using distributed register filesASCENIUM INC·Filed 2022·Application pending·0 cites
- 2546US2022214885A1Parallel processing architecture using speculative encodingASCENIUM INC·Filed 2022·Application pending·0 cites
- 2645US2024028340A1Parallel processing architecture with bin packingASCENIUM INC·Filed 2023·Application pending·0 cites
- 2745US2022075740A1Parallel processing architecture with background loadsASCENIUM INC·Filed 2021·Application pending·0 cites
- 2844US2025341970A1Global memory disambiguation for a parallel architecture with compute slicesASCENIUM INC·Filed 2025·Application pending·0 cites
- 2944US2022075627A1Highly parallel processing architecture with shallow pipelineASCENIUM INC·Filed 2021·Application pending·0 cites
- 3040US2025306930A1Local memory disambiguation for a parallel architecture with compute slicesASCENIUM INC·Filed 2025·Application pending·0 cites
- 3139US2025085970A1Semantic ordering for parallel architecture with compute slicesASCENIUM INC·Filed 2024·Application pending·0 cites
- 3239US2022075651A1Highly parallel processing architecture with compilerASCENIUM INC·Filed 2021·Application pending·0 cites
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