Assignee
TOLL BRET L
US·5 granted patents·4 pending applications·11 citations·filing 2011–2013
Top patents by PatentIndex Score
9 records- 0187US9354877B2Systems, apparatuses, and methods for performing mask bit compressionTOLL BRET L·Filed 2011·Granted May 31, 2016·9 cites·20 claims
- 0268US9244687B2Packed data operation mask comparison processors, methods, systems, and instructionsTOLL BRET L·Filed 2011·Granted Jan 26, 2016·2 cites·25 claims
- 0350US9600285B2Packed data operation mask concatenation processors, methods, systems and instructionsTOLL BRET L·Filed 2011·Granted Mar 21, 2017·0 cites·24 claims
- 0449US10564966B2Packed data operation mask shift processors, methods, systems, and instructionsTOLL BRET L·Filed 2011·Granted Feb 18, 2020·0 cites·29 claims
- 0544US9760371B2Packed data operation mask register arithmetic combination processors, methods, systems, and instructionsTOLL BRET L·Filed 2011·Granted Sep 12, 2017·0 cites·27 claims
- 0644US2015186140A1Opcode trappingTOLL BRET L·Filed 2013·Application pending·0 cites
- 0743US2015095614A1Apparatus and method for efficient migration of architectural state between processor coresTOLL BRET L·Filed 2013·Application pending·0 cites
- 0842US2014068227A1Systems, apparatuses, and methods for extracting a writemask from a registerTOLL BRET L·Filed 2011·Application pending·0 cites
- 0940US2012185670A1Scalar integer instructions capable of execution with three registersTOLL BRET L·Filed 2011·Application pending·0 cites
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