Assignee
SENOO MASARU
JP·14 granted patents·1 pending application·36 citations·filing 2008–2013
Top patents by PatentIndex Score
15 records- 0184US9064711B2Semiconductor device and method for fabricating semiconductor deviceSENOO MASARU·Filed 2011·Granted Jun 23, 2015·8 cites·6 claims
- 0281US9035415B2Vertical semiconductor device comprising a resurf structureSENOO MASARU·Filed 2011·Granted May 19, 2015·6 cites·3 claims
- 0378US9178014B2Semiconductor deviceSENOO MASARU·Filed 2012·Granted Nov 3, 2015·5 cites·3 claims
- 0476US8242535B2IGBT and method of producing the sameSENOO MASARU·Filed 2009·Granted Aug 14, 2012·5 cites·4 claims
- 0569US8674511B2Method of forming a semiconductor device with a contact pad on a sloped silicon dioxide surfaceSENOO MASARU·Filed 2012·Granted Mar 18, 2014·2 cites·4 claims
- 0669US8476732B2Semiconductor deviceSENOO MASARU·Filed 2008·Granted Jul 2, 2013·4 cites·4 claims
- 0766US9048085B2Semiconductor deviceSENOO MASARU·Filed 2013·Granted Jun 2, 2015·2 cites·2 claims
- 0864US9412809B2Semiconductor device and manufacturing method thereofSENOO MASARU·Filed 2013·Granted Aug 9, 2016·1 cites·6 claims
- 0961US9190503B2IGBT and method of manufacturing the sameSENOO MASARU·Filed 2011·Granted Nov 17, 2015·1 cites·6 claims
- 1058US8735974B2Semiconductor devicesSENOO MASARU·Filed 2010·Granted May 27, 2014·1 cites·9 claims
- 1158US8169087B2Semiconductor deviceSENOO MASARU·Filed 2009·Granted May 1, 2012·1 cites·7 claims
- 1251US2010258943A1Semiconductor deviceSENOO MASARU·Filed 2008·Application pending·0 cites
- 1347US8952553B2Semiconductor device with stress relaxation during wire-bondingSENOO MASARU·Filed 2009·Granted Feb 10, 2015·0 cites·9 claims
- 1439US9000478B2Vertical IGBT adjacent a RESURF regionSENOO MASARU·Filed 2012·Granted Apr 7, 2015·0 cites·14 claims
- 1539US8610204B2Semiconductor deviceSENOO MASARU·Filed 2011·Granted Dec 17, 2013·0 cites·2 claims
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