Assignee

PANDEY AWARTIKA

US·2 granted patents·21 citations·filing 2010–2012

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2 records

0190US8176452B2Method and apparatus for circuit partitioning and trace assignment in circuit designPANDEY AWARTIKA·Filed 2010·Granted May 8, 2012·12 cites·21 claims
0288US8458639B2Circuit partitioning and trace assignment in circuit designPANDEY AWARTIKA·Filed 2012·Granted Jun 4, 2013·9 cites·21 claims

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