Assignee
JUENGLING WERNER
US·37 granted patents·3 pending applications·216 citations·filing 2004–2012
Top patents by PatentIndex Score
40 records- 0199US8501607B1FinFET alignment structures using a double trench flowJUENGLING WERNER·Filed 2012·Granted Aug 6, 2013·64 cites·17 claims
- 0292US8293602B2Method of fabricating a finFET having cross-hair cellsJUENGLING WERNER·Filed 2010·Granted Oct 23, 2012·12 cites·19 claims
- 0391US8829602B2Integrated circuits and transistor design thereforJUENGLING WERNER·Filed 2011·Granted Sep 9, 2014·9 cites·26 claims
- 0491US8294511B2Vertically stacked fin transistors and methods of fabricating and operating the sameJUENGLING WERNER·Filed 2010·Granted Oct 23, 2012·10 cites·30 claims
- 0590US8669159B2Devices with cavity-defined gates and methods of making the sameJUENGLING WERNER·Filed 2011·Granted Mar 11, 2014·9 cites·22 claims
- 0690US8598653B2FinFET having cross-hair cellsJUENGLING WERNER·Filed 2012·Granted Dec 3, 2013·9 cites·25 claims
- 0790US8097910B2Vertical transistorsJUENGLING WERNER·Filed 2010·Granted Jan 17, 2012·8 cites·14 claims
- 0889US8148247B2Method and algorithm for random half pitched interconnect layout with constant spacingJUENGLING WERNER·Filed 2010·Granted Apr 3, 2012·7 cites·20 claims
- 0987US8546876B2Systems and devices including multi-transistor cells and methods of using, making, and operating the sameJUENGLING WERNER·Filed 2008·Granted Oct 1, 2013·11 cites·24 claims
- 1087US8148776B2Transistor with a passive gateJUENGLING WERNER·Filed 2008·Granted Apr 3, 2012·13 cites·8 claims
- 1186US8921899B2Double gated 4F2 dram CHC cell and methods of fabricating the sameJUENGLING WERNER·Filed 2010·Granted Dec 30, 2014·6 cites·20 claims
- 1286US8537608B2Data cells with drivers and methods of making and operating the sameJUENGLING WERNER·Filed 2012·Granted Sep 17, 2013·5 cites·18 claims
- 1386US8207583B2Memory device comprising an array portion and a logic portionJUENGLING WERNER·Filed 2010·Granted Jun 26, 2012·5 cites·11 claims
- 1485US8399920B2Semiconductor device comprising a transistor gate having multiple vertically oriented sidewallsJUENGLING WERNER·Filed 2007·Granted Mar 19, 2013·7 cites·12 claims
- 1581US8916912B2Semiconductor device comprising a transistor gate having multiple vertically oriented sidewallsJUENGLING WERNER·Filed 2012·Granted Dec 23, 2014·3 cites·6 claims
- 1681US8772840B2Memory device comprising an array portion and a logic portionJUENGLING WERNER·Filed 2012·Granted Jul 8, 2014·3 cites·15 claims
- 1780US8076229B2Methods of forming data cells and connections to data cellsJUENGLING WERNER·Filed 2008·Granted Dec 13, 2011·5 cites·18 claims
- 1879US8101497B2Self-aligned trench formationJUENGLING WERNER·Filed 2008·Granted Jan 24, 2012·4 cites·26 claims
- 1976US8557656B2Cross-hair cell based floating body deviceJUENGLING WERNER·Filed 2012·Granted Oct 15, 2013·3 cites·20 claims
- 2075US8617953B2Memory having a vertical access deviceJUENGLING WERNER·Filed 2010·Granted Dec 31, 2013·3 cites·19 claims
- 2174US8503228B2Data cells with drivers and methods of making and operating the sameJUENGLING WERNER·Filed 2011·Granted Aug 6, 2013·2 cites·20 claims
- 2273US8866254B2Devices including fin transistors robust to gate shorts and methods of making the sameJUENGLING WERNER·Filed 2008·Granted Oct 21, 2014·4 cites·22 claims
- 2372US8450785B2Systems and devices including multi-gate transistors and methods of using, making, and operating the sameJUENGLING WERNER·Filed 2011·Granted May 28, 2013·2 cites·18 claims
- 2471US9190494B2Systems and devices including fin field-effect transistors each having U-shaped semiconductor finJUENGLING WERNER·Filed 2008·Granted Nov 17, 2015·4 cites·21 claims
- 2570US8278703B2Cross-hair cell based floating body deviceJUENGLING WERNER·Filed 2010·Granted Oct 2, 2012·2 cites·14 claims
- 2666US8497550B2Multi-level DRAM cell using CHC technologyJUENGLING WERNER·Filed 2011·Granted Jul 30, 2013·2 cites·3 claims
- 2765US8962401B2Double gated 4F2 dram CHC cell and methods of fabricating the sameJUENGLING WERNER·Filed 2012·Granted Feb 24, 2015·1 cites·20 claims
- 2862US8416610B2Systems and devices including local data lines and methods of using, making, and operating the sameJUENGLING WERNER·Filed 2010·Granted Apr 9, 2013·2 cites·20 claims
- 2961US8629483B2Locally 2 sided CHC DRAM access transistor structureJUENGLING WERNER·Filed 2011·Granted Jan 14, 2014·1 cites·6 claims
- 3056US2007152340A1Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitryJUENGLING WERNER·Filed 2007·Application pending·0 cites
- 3155US8877639B2Method and algorithm for random half pitched interconnect layout with constant spacingJUENGLING WERNER·Filed 2012·Granted Nov 4, 2014·0 cites·19 claims
- 3254US8592898B2Vertical gated access transistorJUENGLING WERNER·Filed 2011·Granted Nov 26, 2013·0 cites·10 claims
- 3353US8536631B2Data cells and connections to data cellsJUENGLING WERNER·Filed 2011·Granted Sep 17, 2013·0 cites·21 claims
- 3452US8482046B2Concentric or nested container capacitor structure for integrated circuitsJUENGLING WERNER·Filed 2011·Granted Jul 9, 2013·0 cites·20 claims
- 3552US7335964B2Semiconductor structuresJUENGLING WERNER·Filed 2005·Granted Feb 26, 2008·0 cites·7 claims
- 3651US8836023B2Memory device with recessed construction between memory constructionsJUENGLING WERNER·Filed 2011·Granted Sep 16, 2014·0 cites·22 claims
- 3750US2005263794A1Integrated circuitryJUENGLING WERNER·Filed 2005·Application pending·0 cites
- 3846US8760950B2Digit line equilibration using access devices at the edge of sub-arraysJUENGLING WERNER·Filed 2011·Granted Jun 24, 2014·0 cites·15 claims
- 3941US9553193B2Double gated fin transistors and methods of fabricating and operating the sameJUENGLING WERNER·Filed 2010·Granted Jan 24, 2017·0 cites·16 claims
- 4041US2005280060A1Concentric or nested container capacitor structure for integrated cicuitsJUENGLING WERNER·Filed 2004·Application pending·0 cites
Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →