Assignee

ISHII YUICHIRO

JP·2 granted patents·25 citations·filing 2011–2011

Technology mixG11C2 H10D1 Y10S1

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2 records

0188US8188549B2Semiconductor memory device having layout area reducedISHII YUICHIRO·Filed 2011·Granted May 29, 2012·11 cites·3 claims
0287US8514612B2Semiconductor memory deviceISHII YUICHIRO·Filed 2011·Granted Aug 20, 2013·14 cites·8 claims

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